Plasma reactors are widely used in processing substrates such as semiconductor wafers in the fabrication of semiconductor integrated circuits. Two related fabrication processes for integrated circuits are plasma etching and plasma-enhanced chemical vapor deposition (CVD). In both these processes, a processing gas is admitted into a vacuum chamber and is excited into its plasma state. Conventionally, the plasma excitation has been performed by capacitively coupling RF energy through opposed electrodes, but more recent developments have emphasized a combination of capacitive coupling and inductive coupling through coils at the side of the chamber. The coils are placed away from the substrate and generate a plasma in a source region. The RF power applied to the pedestal in etching creates a DC bias voltage across the sheath of the plasma next to the wafer and thus controls the energy of ions expelled from the plasma to the wafer. The plasma-excited processing gas and its ions and radicals interact with the substrate. In etching, the processing gas removes parts of the substrate. On the other hand, in chemical vapor deposition, part of the processing gas deposits on the substrate.
In many types of plasma processing, the active gas is entrained in an inactive carrier gas, and both gases are excited into a plasma. A carrier gas is used for a number of reasons. The additional gas produces a higher chamber pressure and thus helps to sustain the plasma above a critical minimum pressure. The carrier gas acts as a diluent and promotes uniformity. The unreactive carrier gas balances the electro-negativity of the plasma. In reactive ion etching, the energy of the argon ions impinging upon the substrate helps to activate the reaction between the bonded atoms of the substrate and the active components of the plasma gas. Argon is the usual carrier gas in etching, but helium is another common carrier gas.
Advanced semiconductor integrated circuits have narrow limits of layer thicknesses and similar parameters. Accordingly, one of the most critical measures of the utility of a new process or of an old process practiced on a new tool is the uniformity of the process across the wafer. For example, what is the difference in the etching rate between the center and the edge of the wafer. A concomitant concern, not further discussed here, is the uniformity or reproducibility between wafers. Uniformity is considered as a statistical problem with random distributions having a median value but with long tails about the median. The median value .mu. of the distribution is not usually a problem since the process timing can usually be adjusted. However, the standard deviation .sigma. (here defined simply as the average deviation from the median) does present a problem. For integrated circuits having millions of devices and requiring hundreds of steps to manufacture, a failure of any one of those devices caused by any one of the steps will produce a defective device. As a result, if a process produces for some fabrication parameter a measured mean .mu. and standard deviation .sigma., and .mu.+.sigma. and .mu.-.sigma. fall well within the predicted window of operability for the device, the statistics may be totally unsatisfactory if the statistics over the entire device and process require a confidence level of, for example, 5.sigma. to attain a low enough defect level. That is, the satisfactory device parameters must fall between .mu.+5.sigma. and .mu.-5.sigma.. It is for reasons like these that .sigma. must be reduced and why uniformities over the wafer of 5% or even 1% are being required.
The increasing demands for uniformity have been occurring at the same time that wafer size has been increasing because of the economies of scale occurring in the production of the larger wafers. Over the past ten years, wafer sizes have been increasing from 100 mm to 150 mm, and now the current standard for high-capacity production is 200 mm. Currently, much development effort is being expended on equipment for 300 mm wafers, which are expected to reach production lines in a few years. The uniformity requirements remain for the larger wafers. Not only are the statistics unfavorable for the larger areas, but there is an economic desire to restrict the volume of the larger chambers because of the expensive clean room floor space they occupy. That is, edge effects can no longer be economically reduced by simply increasing the volume of the chamber.
Processing gas is usually injected into a plasma processing chamber through one or more ports arranged in a somewhat similar geometry. For example, the counter electrode facing a pedestal electrode holding the wafer may be a showerhead electrode having a large number of small apertures distributed over the area of the showerhead generally corresponding to the area of the wafer and directed at the wafer. In another example, a gas distribution ring may surround the area between the two electrodes and have multiple apertures directing the gas toward the intermediate area. However, prior art is known in which multiple gas ports of substantially different geometries are used, as disclosed by Collins in U.S. Pat. No. 5,556,501 and in U.S. patent application, Ser. No. 08/734,797, filed Oct. 23, 1996. Tahara et al. have disclosed in U.S. Pat. No. 5,356,515 an oxide etch chamber in which the showerhead is supplied with CF.sub.4, CHF.sub.3, CO, and Ar while an annular port surrounding the showerhead is supplied only with CO.